The present invention relates to semiconductor storage technology, and more particularly to non-volatile memories which are electrically writable and erasable. Specifically, it relates to techniques which are effective when utilized for a non-volatile memory and a microcomputer including the non-volatile memory.
An EEPROM (Electrically Erasable and Programmable Read Only Memory) is a non-volatile memory, and it is electrically rewritable. To the contrary, however, this feature has been a problem because data to be conserved might be rewritten. For the protection of the data of a non-volatile memory, accordingly, there has been proposed a method wherein a bit for security is provided and wherein access from outside the memory is inhibited depending upon the status of this bit. Such a data protection system based on the security bit is stated in, for example, "Electronic Design," Mar. 3, 1983, pp. 123-128.
More specifically, a write-only security register including a non-volatile memory cell which is isolated from ordinary memory cells intended for rewriting data is disposed, and access to the memory cells is inhibited depending upon the status of the specified bit of the register. In this case, the security register is so constructed that it can erase data only at the time of the overall and simultaneous erase operations of the memory cells. Thus, after protection information indicating the protection of the data in the memory cells has been written into the security register, the memory cells cannot be accessed without destroying the data thereof, and the data can be kept secret.
With this method, however, the information in the security register is lost by the overall and simultaneous erasure of the memory cells, to establish the same status as an initial status. It has therefore been impossible to eliminate the apprehension that the memory will be illegally used after the overall and simultaneous erasure. The reason is that, after the initialization of the memory by the overall and simultaneous erasure, the memory can be reused by writing any false data. This has posed a problem in a case where important information such as money information is stored in an application to, for example, a cash card. Meanwhile, since the EEPROM requires long write/ erase times, increase in the storage capacity thereof has made the overall erase function of the memory cells indispensable to shortening a test time. It has accordingly been a subject that the overall and simultaneous erasure is compatible with the inhibition of the unlawful initialization.
There has also been proposed an EEPROM wherein a column latch circuit is disposed every data line of memory cells, thereby making it possible to write data items collectively every row address (refer to "Hitachi Hyoron- (Hitachi Review), Vol. 68, No. 7," pp. 75-78 issued on July 25, 1986 by Hitachi Hyoron- Sha). The column latch makes it possible to simultaneously write or rewrite a plurality of data items, and has been utilized only for efficaciously shortening write/rewrite times per unit data.